Articles
  • Strained silicon substrate technologies for enhancement of transistor performance 
  • Peter Mei* and Yee-Chia Yeo
  • Globitech Incorporated, Sherman, TX 75092, USA *Department of Electrical & Computer Eng., National University of Singapore, Singapore
Abstract
Strain-induced improvement of electron or hole mobility is a very attractive way of enhancing the speed performance of integrated circuits in addition to device scaling. This paper reviews several promising substrate technologies for the exploitation of strain-induced effects. Strained silicon substrates incorporating layer structures such as strained-Si on a relaxed SiGe buffer layer, strained-Si-on-insulator, and strained-Si/SiGe-on-insulator, are examined. Technical challenges for these substrate technologies are investigated, and their relative merits are compared.

Keywords: Strain, transistor, CMOS, substrate

This Article

  • 2004; 5(3): 261-263

    Published on Sep 30, 2004